The continuous trend in the semiconductor industry involves achieving higher and higher circuit density with increasing numbers of transistors, lower operating voltages, and higher access speeds. The trend is fueled by efforts in scaling down device dimensions (e.g., at sub-micron levels).
Transistors undergo scaling, in part, by shrinking the transistor gate dielectric. For example, silicon dioxide gate insulating films with a thickness of 2 nm are available. While the relatively thin gate insulating films increase operation speeds, other problems are undesirably created.
But generally as transistors shrink, leakage current increases. Leakage inhibits the performance of a microelectronic device. Power consumption is an important concern due to gate leakage. In electronic devices, it is typically desirable to reduce the amount of power that is consumed by a microelectronic device. This is because in battery powered electronic devices it is typically desirable to reduce the amount of power consumed by the microelectronic device in order to extend the time the electrical device may be powered by a battery. Managing gate leakage current is an important concern in making reliable high-speed operation transistors. Thus, within the context of scaling, managing gate leakage current is an increasingly important factor in the semiconductor industry.
Metal oxide semiconductor field-effect transistors (MOSFETs) with thin gate dielectrics made from silicon dioxide often experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-K dielectric materials instead of silicon dioxide can reduce gate leakage. However, high-K dielectric materials may not be compatible with polysilicon. When relatively thin high-K dielectric layers contain an oxide, the layers may undesirably have oxygen vacancies and excess impurity levels. Oxygen vacancies raise concerns because they permit undesirable interaction between the high-K dielectric layer and the gate electrode. And when the gate electrode contains polysilicon, such interaction may alter the work function of the gate electrode or cause the device to short through the dielectric. In such instances, it is desirable to use metal gate electrodes in microelectronic devices that contain high-K gate dielectric layers since metal gate electrodes are typically more compatible with high-K gate dielectrics than polysilicon.
Metal gate electrodes have several desirable features compared to polysilicon including, fewer poly depletion effects if not the complete elimination of poly depletion effects and consequent improvement in gate control over the channel. However, metal gate electrodes have a constant or uniform work function across the microelectronic device. In other words, the work function of the gate electrode is constant from one source/drain region across the channel region to the other source/drain region.
When a high-K dielectric layer is initially formed, it may have a slightly imperfect molecular structure. To repair the high-K dielectric layer, it may be necessary to anneal at a relatively high temperature. However, the materials used in the metal gate electrode typically cannot tolerate the high temperatures associated with annealing the high-k dielectric layer. As a result, process flows are employed such that the high-k gate dielectric layer may be annealed without damaging the metal gate electrode. In particular, a so-called gate last process is often employed to make metal gate/high-K gate dielectric structures. The gate last process refers to the order of forming the metal gate relative to the polysilicon deposition act. The gate last process is sometimes known as the replacement gate process.
A problem with the gate last process is the enormous cost compared to a gate first process. In CMOS technology, while the gate first process is much less expensive than a gate last process, the gate first process undesirably induces large Vth of the pFET. This is because the high temperature of the annealing act creates oxygen vacancies (positive charges) in the high-K gate dielectric. The large Vth can be mitigated by oxidizing the structure in an oxygen containing atmosphere as oxidation reduces Vth of pFET.